In a typical copper Damascene process, the formation of the desired conductive routes generally begins with a thin physical vapor deposition (PVD) of the metal, followed by a thicker electrofill layer (which is formed by electroplating). The PVD process is typically sputtering. In order to maximize the size of the wafer's useable area (sometimes referred to herein as the “active surface region”) and, thereby, maximize the number of integrated circuits produced per wafer), the electrofilled metal must be deposited to very near the edge of the semiconductor wafer. Thus, it is necessary to allow physical vapor deposition of the metal over the entire front side of the wafer. As a byproduct of this process step, PVD metal typically coats the front edge area outside the active circuit region, as well as the side edge, and to some degree, the backside.
Electrofill of the metal is much easier to control, since the electroplating apparatus can be designed to exclude the electroplating solution from undesired areas such as the edge and backside of the wafer. One example of plating apparatus that constrains electroplating solution to the wafer active surface is the SABRE™ clamshell electroplating apparatus available from Novellus Systems, Inc. of San Jose, Calif. and described in U.S. Pat. No. 6,156,167 “Clamshell Apparatus For Electrochemically Treating Semiconductor Wafers,” by E. Patton et al., and filed Nov. 13, 1997, which is herein incorporated by reference in its entirety.
The PVD metal remaining on the wafer edge after electrofill is undesirable for various reasons. For example, the PVD metal on the wafer edge is not suitable for subsequent depositions and tends to flake off generating undesirable particles. By contrast the PVD metal on the active interior region of the wafer is simply covered with thick and even electrofill metal and planarized by CMP down to the dielectric. This flat surface, which is mostly dielectric, is covered with a barrier layer, such as silicon nitride or silicon carbide, that both adheres well to the dielectric and aids in the adhesion of subsequent layers. Unfortunately, the barrier layer, which like the residual PVD metal layers deposits over the wafer edge area, is often thin and uneven and therefore may allow migration of the metal into the dielectric. This problem is especially important when the metal is copper.
To address these problems, semiconductor equipment may have to allow etching of the unwanted residual metal layers. Various difficulties will be encountered in designing a suitable etching system. For example, one of the main constraints of edge bevel removal (EBR) is a relatively long processing time. Smaller node technology allows significant reduction of plating time for thin films. In order to realize the throughput gain, it is highly desirable to reduce duration of all non-plating processes, such as EBR. Additional problems include controlling the etching area during the EBR process. It is desirable to minimize losses of electro-filled metal in the active area of the wafer while completely removing the surrounding bevel (i.e. to reduce “taper width” of the deposited metal). Overall, improved edge bevel removal methods and apparatuses are desired. Commonly assigned U.S. Pat. No. 8,419,964 “Apparatus And Method For Edge Bevel Removal Of Copper From Silicon Wafers,” by K. Ganesan et al., and filed Aug. 27, 2008, which is herein incorporated by reference, discloses an apparatus for performing EBR wherein a wafer is supported on a rotatable chuck having support pins and alignment pins. A suitable chuck is described in commonly assigned U.S. Pat. No. 6,537,416 “Wafer Chuck For Use In Edge Bevel Removal Of Copper From Silicon Wafers,” by S. Mayer et al., and filed Apr. 25, 2000, which is herein incorporated by reference. During wafer centering, a wafer slides on rubber support pins which can lead to wear and particle problems. It would be desirable to extend the wear of the support pins and reduce particle generation during wafer centering.